Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory. One type is RAM (random-access memory). This is typically used as main memory in a computer environment. RAM refers to read and write memory; that is, you can both write data into RAM and read data from RAM. This is in contrast to ROM, which permits you only to read data. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost.
Computers almost always contain a small amount of read-only memory (ROM) that holds instructions for starting up the computer. Unlike RAM, ROM cannot be written to. An EEPROM (electrically erasable programmable read-only memory) is a special type non-volatile ROM that can be erased by exposing it to an electrical charge. Like other types of ROM, EEPROM is traditionally not as fast as RAM. EEPROM comprise a large number of memory cells having electrically isolated gates (floating gates). Data is stored in the memory cells in the form of charge on the floating gates. Charge is transported to or removed from the floating gates by programming and erase operations, respectively.
Yet another type of non-volatile memory is a Flash memory. A Flash memory is a type of EEPROM that can be erased and reprogrammed in blocks instead of one byte at a time. Many modern PCS have their BIOS stored on a flash memory chip so that it can easily be updated if necessary. Such a BIOS is sometimes called a flash BIOS. Flash memory is also popular in modems because it enables the modem manufacturer to support new protocols as they become standardized.
A typical Flash memory comprises a memory array that includes a large number of memory cells arranged in row and column fashion. Each of the memory cells includes a floating gate field-effect transistor capable of holding a charge. The cells are usually grouped into blocks. Each of the cells within a block can be electrically programmed in a random basis by charging the floating gate. The charge can be removed from the floating gate by a block erase operation. The data in a cell is determined by the presence or absence of the charge in the floating gate.
A synchronous DRAM (SDRAM) is a type of DRAM that can run at much higher clock speeds than conventional DRAM memory. SDRAM synchronizes itself with a CPU's bus and is capable of running at 100 MHZ, about three times faster than conventional FPM (Fast Page Mode) RAM, and about twice as fast EDO (Extended Data Output) DRAM and BEDO (Burst Extended Data Output) DRAM. SDRAM's can be accessed quickly, but are volatile. Many computer systems are designed to operate using SDRAM, but would benefit from non-volatile memory.
Further, as the geometries and cost of integrated circuit memories continues to be reduced, the costs associated with testing the memories is becoming a more significant component of the total manufacturing cost. Specifically, before delivery to end users, each memory chip must be tested to ensure that it is functioning properly. Typically, the entire memory array must be tested.
For example, a common testing procedure for a memory connected to a memory tester is to first have the tester send a command to the memory to erase all of its bits to “1”. The tester then reads the memory cells to verify that they are all “1”. Next, zeros are written to all of the bits of the memory and the cells are read in order to verify that they are all “0”. Then, all of the bits of the memory are erased, a checkerboard pattern is written to the memory and the cells are read in order to verify that the checkerboard pattern is present. Finally, all of the bits of the memory are erased, an inverted checkerboard pattern is written to the memory, and the cells are read in order to verify that the inverted checkerboard pattern is present. This testing procedure is a good way to find out if any of the bits of the memory are shorted to an adjacent bit, to a high level, or to a low state, or if there are any other problems.
Because the cost of testing has becoming a significant component of the total manufacturing cost of memory chips, testing using compressed data lines can be implemented. See U.S. Pat. No. 5,787,097 entitled “Output Data Compression Scheme for Use in Testing IC Memories,” issued Jul. 28, 1998. This patent describes a system for compressing data during a test operation so that multiple memory devices can be simultaneously tested using a common tester. That is, each memory device uses a subset of its data output connections.
To conduct test operations on a memory device, the memory device is placed in a test mode. Because the test mode should not be entered accidentally, an electronic key is often used to restrict access to test modes. For example, a high voltage may be required on a specific input connection to enter a test mode. Further, a test mode code can be provided on data input connections to instruct the memory device which test is to be selected. If the memory is operated in a compressed mode, complicated circuitry is needed to detect the test mode codes on the data connections.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a non-volatile memory device that can operate in a compressed data mode and easily select between different test modes.